Method and system for protecting a stacked gate edge in a semiconductor device from self-aligned source (sas) etch in a semiconductor device

ABSTRACT

A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

This application is a continuation of application Ser. No. 08/500,422,filed on Jul. 11, 1995, abandoned, which is a divisional of U.S. Ser.No. 433,261, now U.S. Pat. No. 5,534,455 filed on May 2, 1995; which isa Continuation-in-part of U.S. Ser. No. 233,774, now U.S. Pat. No.5,470,773 filed on Apr. 25, 1994.

FIELD OF THE INVENTION

The present invention relates to semiconductor processing techniques andmore particularly to self-aligned source (SAS) processing techniques.

BACKGROUND OF THE INVENTION

In producing semiconductors and more particularly FLASH EPROM devices,increasing the density of the device significantly enhances performanceas well as cost effectiveness of the device. The typical way increasingthe density has been accomplished is through the use of a so-called selfaligned source (GAS) etching technique which provides for the properformation of the FLASH dell. An example of this type of technique isdisclosed in U.S. Pat. No. 5,120,671 entitled "PROCESS FOR SELF ALIGNINGA SOURCE REGION WITH A FIELD OXIDE REGION AND A POLYSILICON GATE".

The above-identified patent discloses a method for forming a sourceregion which is self-aligned with the poly word line as well as anapparatus formed thereby. In the patent, the end edges of the fieldoxide regions are vertically aligned with the poly word line with nobird's beak encroachment and corner rounding effect remaining in whatwill become the source region. The source region, formed between theends of the field oxide regions of neighboring cells, is thusself-aligned with both the field oxide regions and the poly gate wordlines. This self-alignment of the source region allows closer placementof poly word lines without any decrease in source width which thusrequires less physical separation between (i.e., allows closer placementof) one memory cell to the next memory cell. Reduced cell size andgreater overall device density is thus achieved.

In this example, the SAS etch is used after a stacked gate etch as a wayto reduce overall cell size in a FLASH EPROM process. However, duringthe SAS etch, the stacked gate edge is exposed to the SAS etch, whichhas a significant negative impact on the tunnel oxide integrity. Inaddition, the building implants which consist mainly of the sourcediffusion implant are done after the SAS etch. Since the SAS etch has atendency to etch away or gouge away silicon under the source region, theimplant profiles might not be uniform at the source and may change theprofile of the surface source that overlaps below the stacked gate. Inthat case, the erase integrity and erase distribution of the FLASH cellmay be significantly degraded. As is well known, if the overlap area istoo great, source coupling may be higher than and interfere with theerase operation. If the overlap area is too small, there may not beenough area for erasure. Typically due to the severity of SAS overetch,erase is significantly impeded due to the lack of sufficient doseunderneath the source overlap region.

Accordingly, what is needed is a system for ensuring that the overallcell size of semiconductor is reduced which doesn't have a negativeimpact on the tunnel oxide integrity of the device. In addition, thesystem should be one in which the implant profiles are uniform at thesource overlap region, thereby ensuring cell integrity.

The present invention addresses these needs.

SUMMARY OF THE INVENTION

The present invention discloses a method and system for protecting astacked gate edge of a semiconductor device. The method comprises thestep of providing the stacked gate edge on the semiconductor device,performing the source implant dose to ensure uniform profile prior toSAS etch, providing an oxide or polysilicon spacer formation on thestacked gate edge prior to self-aligned source etch, providing a selfaligned source etch of the semiconductor device, and providing a voltagesource connection implant. In so doing, the stacked gate edge isprotected thereby providing for tunnel oxide integrity and also auniform source junction profile which is performed before the SAS etchand which is also independent of gouge and damage more than thoseprovided by previously known processes. Further, the step of providingthe source connection implant after the SAS etch eliminates severalsteps, including an oxidation step and masking step. The reduction inprocessing steps helps reduce processing time and cost.

The present invention has particular application in a FLASH EPROM celltechnology. With the present invention, the increased cell densityassociated with the FLASH cell is maintained, while the above-mentionedproblems with tunnel oxide integrity and source junction profile areeliminated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a portion of a memory device.

FIGS. 2-4 are side views of the memory device of FIG. 1.

FIG. 4a is a sectional view of the memory device of FIG. 1.

FIG. 5 is a cutaway perspective view of the source side view of aconventional FLASH cell after the SAS etch showing the source profileprovided if source implant is after self aligned source (SAS) etch inthe prior art. Note that, since the implants are performed after the SASetch, their profiles are extremely sensitive to silicon gouge anddamage, thus erase behavior is very inadequate.

FIGS. 6-10 are cutaway perspective views of a FLASH cell as it proceedsthrough a conventional (prior art) process. Both flash memory cell andthe supporting peripheral transistors are shown.

FIG. 11 is a simple flow chart of the process of providing a FLASH cellin accordance with the present invention.

FIG. 12 is a detailed flow chart of the process of FIG. 11.

FIG. 13 is a cutaway view of the FLASH cell before the SAS etch inaccordance with the process flow of the present invention.

FIG. 14 is a cutaway view of the FLASH cell after the SAS etch.

FIG. 15 is a flow diagram of an alternate embodiment of the processshown in FIG. 12.

DETAILED DESCRIPTION

The present invention is related to an improvement in the processing ofa semiconductor circuit, particularly a FLASH EPROM cell. The followingdescription is presented to enable one of ordinary skill in the art tomake and use the invention and is provided in the context of a patentapplication and its requirements. Various modifications to the preferredembodiment will be readily apparent to those skilled in the art and thegeneric principles herein may be applied to other embodiments. Thus, thepresent invention is not intended to be limited to the embodiment shownbut is to be accorded the widest scope consistent with the principlesand features described herein.

With reference to the drawings, FIG. 1 illustrates a top view of aportion of a memory device formed in accordance with a conventionalprocess. In this process, field oxide regions 31 and 33 are formed bygrowing oxide between parallel rows of nitride regions 18 to form thefield oxide regions 31 and 33 as continuous lines across the source line12 formed in the openings of a latticework of nitride regions 18. Alayer of polysilicon is then deposited over the field oxide regions 31and 33. After placing a photoresist mask over the polysilicon, theportions of the polysilicon left exposed are etched away. The remainingportions of polysilicon are poly word lines 9 and 11, which run parallelto source line 12.

Etching the polysilicon to form poly word lines 9 and 11 exposes theunderlying field oxide regions 31 and 33 in the region of source line12. Source mask 41 is then placed over the memory device and the oxideregions 31 and 33 are then etched away where they were exposed by theetching of poly word lines 9 and 11. This field oxide etch, which uses ahigh selectivity etch, as is discussed in more detail below, reducesfield oxide regions 31 and 33 into separate field oxide regions 13, 15,17 and 19. More importantly, this field oxide etch aligns field oxideregions 13 and 15, as well as 17 and 19, with the edges of poly wordlines 9 and 11. Thus, when source implantation occurs it is self-alignedto the coincident edges of the field oxide and the polysilicon regions.

It is important to note that the source mask 41 is not used to align thesource region implantation with the edges of the poly word lines. Thesource mask 41 is placed on the memory device to protect (duringimplantation) the portions of the field oxide regions 31 and 33 whichreside on the other side of the poly word lines 9 and 11 from the sourceregion 12 and between which the drain regions 14 will later be formed.

The formation and resulting alignment of field oxide regions 17 and 19with poly word lines 9 and 11 is further shown in side views in FIGS.2-4. Referring now to FIG. 2, field oxide 33 is formed on the siliconsubstrate 29. Polysilicon 35 is then deposited on the field oxide 33. Aphotoresist mask 39 is then placed on top of the polysilicon 35 leavingselect portions of the polysilicon exposed. Note that a direct writetechnique, using for example an electron beam or a laser beam, couldalso be used to create the mask pattern in the photoresist.

Etching the exposed polysilicon 35 through the photoresist mask 39 ofFIG. 2 yields the formation, as shown in FIG. 3, where the onlyremaining polysilicon is that which was protected by the opaque portionsof photoresist mask 39. The remaining polysilicon portions are poly wordlines 9 and 11. Note that FIG. 2 represents a cross-sectional view ofFIG. 1 along line a--a and shows the continuous field oxide layer 33underlying poly word lines 9 and 11.

Forming poly word lines 9 and 11, by etching the exposed polysiliconthrough the mask 39, exposes portions of the underlying field oxide 33.In the preferred embodiment, mask 41 is then placed on the device toprotect the drain regions and then the field oxide portions are etchedaway using a high selectivity oxide etch, as is discussed more fullybelow. Referring now to FIG. 4, after etching field oxide 33, theportions that remain are field oxide regions 17 and 19.

Referring to FIG. 4A, what is shown is the cross section of the activecell region at the same point in the process before the source implant.The source implant is then performed along with a drain implant.

Referring now to FIG. 5, what is shown is an enlarged cutaway diagram ofa FLASH EPROM cell 100 which has been processed in accordance with theprior art and the subsequent source and drain implant. Note that FIG. 5can be thought of as the right half of FIG. 4A with source and drainimplants performed after the SAS oxide etch. This cell 100 comprisesfirst and second polysilicon layers 102 and 103 and oxide region 104therebetween, and a tunnel oxide region 106 between the first polysilicon layer 102 and the silicon area 108. In such a cell, the SAS etch110 could effect the tunnel oxide region 106 with damage induced by theetch as shown by 107 and also could cause gouging of the silicon areawhich would cause a large variation on the implant regions and on thelateral profile of the oxide region 106 under the gate. To morespecifically describe how this might occur, refer now to FIGS. 6 through10, which show the various stages of the operation of the prior artprocess.

Referring to FIG. 6, initially a stacked gate etch is applied to thepolysilicon region 102. Then, thereafter, referring to FIG. 7, an SASmask 202 is placed on top of the device to allow for certain portions ofthe oxide to be masked. Thereafter there is an SAS etch 204 whichessentially removes a portion of the silicon area shown in FIG. 8. InFIG. 9, a first implant 114 is provided typically to reduce the unwantedband-band tunneling current, and a resist strip is applied. As is seenthis implant could be brought to a position well inside the gate area ofthe device. This implant is optional. The second implant is provided toprovide the source/drain regions 112/108 shown in FIG. 10. It is thisimplant and its resultant high surface concentration under the sourceoverlap region that facilitates the proper erasure of the flash code. Asis seen in FIG. 10, the resultant cell could have significant tunneloxide erosion as well as degraded silicon doping due to silicon gougefrom the SAS etch process. A conventional process to fabricate theperipheral transistor then follows to finish off the process.

The present invention addresses these problems by performing thesource/drain implant prior to the SAS etch, and by using a spacerformation to protect the stacked gate edge from exposure to the SASprocess. Since this spacer formation is already inherent in nearly allCMOS processes as described above with reference to FIGS. 1-4, existingprocess techniques do not have to be made significantly more complicatedto provide the protection from SAS etch related problem. Through the useof this spacer formation, the SAS etch does not affect the doped areasnor does it affect the tunnel oxide region.

To more specifically describe the features of the present invention,refer now to FIG. 11, which is a simple flow chart showing the processin accordance with the present invention. Accordingly this processcomprises providing a stacked gate edge, via step 302. Source implant isperformed along with the drain implant, via step 303. The spacerformation is then provided, via step 304. Thereafter, the self-alignedsource etch is provided, via step 306. This way any damage that occursdue to SAS etch is placed away from the stacked gate edge, thus tunneloxide and source doping profiles are both protected.

To describe this process with reference to a preferred embodiment refernow to FIG. 12 which shows a detailed flow chart of the process shown inFIG. 11. Referring now to FIG. 12, what is shown is a flow chart of themethod for protecting the tunnel oxide,.stacked gate edge and sourcejunction function profile of a device. First, the stacked gate etchtakes place, via step 402. Then the resist strip takes place, via step404. Next a thin oxide or oxidation for implant screen is provided, viastep 406.

Thereafter, the double diffused implant (DDI) mask and DDI implant takesplace, via step 408 and another resist strip takes place, via step 410.Thereafter, the modified drain diffusion (MDD) mask and implant takesplace via step 412 by which the source profile is formed along with thedrain profile and another resist strip takes place, via step 413.Thereafter a N-lightly doped drain (LDD) mask and implant and a P-LDDimplant mask and implant is provided, via steps 415 and 416 and anantipunch through (AT) implant is provided, via step 418.

Then the spacer deposition is provided via step 420. Finally, the spaceris etched, via step 422 for spacer formation. This spacer could becomprised of various types of material. At this point, the cross sectionof the core cell 500 looks like that shown in FIG. 13. Accordingly, thestacked gate edge 502 and the tunnel oxide 506 are protected by thespacer formation 504. Thereafter the process for providing SAS etch canoccur. Referring back to FIG. 12, an SAS mask is provided, via step 424.Then the SAS etch can be provided, via step 426. Thereafter the SAS maskis removed and the post-spacer etch oxidation takes place, via step 428.Then the N+ S/D mask and DDI mask (a critical mask) are provided, viastep 430. Finally, the N+ source/drain (S/D) implant and a sourceconnection implant are provided via step 432.

In the conventional process, since the MDD implant is done after the SASetch, the V_(SS) line is automatically connected. In one embodiment ofthis invention, since the MDD implant is done before the SAS etch, anadditional implant is needed to connect the field oxide region andactive region of the source line. In an alternate embodiment, thisadditional implant can be obtained without an extra processing step byusing then N⁺ S/D implant, step 432, to connect the source line from theactual source region and field region that is SAS etched for the V_(ss)line connection. The cross section of the resulting cell 500 will looklike that shown in FIG. 14. In this cell the tunnel oxide integrity isimproved and there is a uniform source region under the source overlaparea since the implant is placed before SAS etch and due to theprotection by the spacer formation 504. Therefore, the source implant isnot provided to a gouged portion of the silicon. Accordingly, a uniformsource region is provided under the gate.

An alternate embodiment to the method of FIG. 12 is shown in FIG. 15.The alternate method follows FIG. 12 through step 426 and the SAS etchstep as shown in FIG. 12B. However, instead of providing spaceroxidation as Shown in step 428 of FIG. 12, the process in FIG. 15continues with step 427 and the source connection implant. After thesource connection implant step, a resist strip occurs (step 429). Theprocess then continues with the provision of a N+ S/D mask in step 431,followed by a N+ S/D implant in step 433.

With this alternate embodiment, some of the processing steps areeliminated. More specifically, there is no oxidation deposition step(e.g., step 428 in FIG. 12A). Also, since there is no oxidation step,the mask used for the SAS etch is also used as the mask for the sourceconnection step (step 427 FIG. 15). Thus, the steps of providing asource connection implant mask and then subsequently removing the maskfollowing the implant are also eliminated. Although the elimination ofthe oxidation step in the alternate embodiment poses a potentialcontamination risk to the structure during the voltage source connectionimplant, the benefits of reducing processing time and thereforeproduction cost by eliminating the step outweigh the risk of possiblecontamination.

Accordingly, in the present invention, the performing of a source/drainimplant and providing of the spacer formation prior to the SAS etchimproves the tunnel oxide region integrity. In addition, through the useof the processes of the present invention, the stacked gate edge isimmune to gouging and source junction profile is improved.

It should be understood that although the present invention has beendescribed in conjunction with a specific type of cell (FLASH EPROM) itshould be recognized by one of ordinary skill in the art that many typesof cells can be produced utilizing this process. It should also berecognized that many types of materials and processes can be utilized toprovide the resist strip, etch, and implants and they would be withinthe spirit and scope of the present invention.

Although the present invention has been described in accordance with theembodiments shown in the figures one of ordinary skill in the art willrecognize there could be variations to those embodiments and thosevariations would be within the spirit and scope of the presentinvention. Accordingly, many modifications may be made by one ofordinary skill in the art without departing from the spirit and scope ofthe present invention, the scope of which is defined solely by theappended claims.

What is claimed is:
 1. A semiconductor device with a protected stackedgate edge to minimize damage to a tunnel oxide region and to maintainsource junction uniformity of a semiconductor device comprising:asemiconductor substrate having the stacked gate edge formed thereon; aspace, the spacer formed on the stacked gate edge; a self aligned source(SAS) on the semiconductor substrate, the SAS formed after the spacer;and a source region included in the SAS, wherein the source region hasbeen substantially undamaged by an SAS etch.
 2. The device of claim 1 inwhich the stacked gate edge comprises an etched stacked gate edge. 3.The device of claim 2 in which the etched stacked gate edge resultsfromproviding a resist strip; providing an oxidation layer; andproviding a mask and an implant on the semiconductor device.
 4. Thedevice of claim 1 in which the spacer formed on the stacked gate edgeresults fromdepositing a spacer material; and etching the spacermaterial to form the spacer.
 5. The device of claim 1 in which the SASresults fromproviding an SAS mask; and etching the SAS mask.
 6. Thesemiconductor device of claim 1, further comprising a source connectionimplant, the source connection implant connecting a source line to afield region of the semiconductor substrate.